Conventional read/write memories, for example static random access memories (SRAMs), as are commonly used in computer systems, lose their stored information when power is removed from the device.
FIG. 1 illustrates a computer system 50 that includes a conventional read/write memory 52. Memory 52 is coupled to a bus 54 that provides a communication path between memory 52 and a processor 56. In general, processor 56 uses memory 52 as a store of data and/or instructions. Computer system 58 may further include one or more functional units 58 which are coupled to bus 54. The functional units 58 may serve a variety of purposes, for example these units may be input/output (I/O) devices which transfer information (e.g., data and/or control signals) to/from processor 56 and/or memory 52. Further, functional unit(s) 58 may be (a) bus bridge(s) which provides a communication path between bus 54 and another bus (not shown), e.g., a system bus, within computer system 50. In such a configuration, bus 54 may serve as a local or processor bus.
FIG. 2 illustrates memory 52 in more detail. Memory 52 generally includes a memory core 60 which is made up of a number of memory cells. The cells of memory core 60 are accessed during read or write operations using bitlines 62 and wordlines 64. Word lines 64 are selected by row decoder 70 in response to address information on address lines 72. Address lines 68 and 72 may be part of bus 54. Similarly, the bitlines 62 are selected using a column decoder 66 which receives and decodes address information from a plurality of address lines 68.
During a memory write operation, data presented on Data In bus 74 may be applied to selected bitlines 62 through write path circuitry 76. (In general, portions of the write path circuitry may be shared by portions of the read path circuitry and, thus, the two are shown as a single block 76.) Individual cells of a column (associated with the selected bitlines) within memory core 60 are selected by appropriate wordlines 64 and the data from the Data In bus 74 is stored in one or more of the memory cells. During a memory read, data is read out of selected memory cells through read path circuitry 76 to a Data Out bus 78. Data In bus 74 and Data Out bus 78 may be the same bus (at least in part) and is/are coupled to bus 54. Read and write operations are controlled using one or more control signals 80 (from bus 54) which are decoded and/or buffered using control circuitry 82 to provide appropriate internal control signals 84 to the read/write path circuits 76.
A typical conventional read/write memory uses SRAM cells as its basic memory cells. Consequently, the memory loses all of its stored information if power is removed or temporarily lost. Accordingly, computer system designers have recognized the need to back up information stored in volatile memories in the event that power is lost, e.g., during a blackout or brownout.
One way to back up a volatile memory such as an SRAM is to transfer the data stored in the SRAM to a separate non-volatile memory before the power is turned off or is about to fail. Unfortunately, such a solution requires that the data be transferred bit-by-bit between the volatile memory and the non-volatile memory. Such a data transfer, which typically occurs over a slow, serial link, cannot accommodate the large amounts of data stored in modern SRAMs (e.g., of the order of 1-4 Mbits) before a complete failure of power.
A more desirable way to prevent loss of information stored in read/write memories is to use non-volatile static random access memory ("NVSRAM"). FIG. 3 illustrates a non-volatile static random access memory cell 100. Memory cell 100, its method of fabrication and its use are the subject of the above-mentioned related patent applications. Briefly, memory cell 100 includes four conventional NMOS transistors: N.sub.1 and N.sub.2 for pull-down and S.sub.1 and S.sub.2 for selecting or transferring data between the cell 100 and the bit lines BL and BL. PMOS pull-up transistors P.sub.1 and P.sub.2 are stacked gate, double-poly transistors with a bottom tunnel dielectric, poly-silicon floating gate and a top poly-silicon control gate. The control gates and floating gates are isolated by a thin poly-to-poly coupling dielectric.
With a normal supply voltage (Vcc-Vss) across terminals V.sub.1 -V.sub.2, memory cell 100 functions exactly like a conventional SRAM cell with unlimited, fast read/write operations. A non-volatile (NV) storage operation (as described in the above related patent applications) is shown in FIG. 4 and is enabled by boosting the supply voltage (Vcc-Vss) to a higher or programming voltage (Vpp-Vnn) approximately 2 (Vcc-Vss), such that E.sub.ox, the field across the tunnel oxide, .gtoreq.8 MV/cm for a specified time (T.sub.STORE) of the order of 1-10 msec. Note that Vnn may be equal to Vss. During this time (T.sub.STORE), electrons are injected by band-to-band not electron (BBHE) injection into the floating gate of the non-conducting stacked gate PMOS transistor while electrons tend to be removed by Fowler-Nordheim (F-N) tunneling from the floating gate of the conducting stacked gate PMOS transistor. Thus, charge is stored on the floating gate of the PMOS transistor undergoing BBHE injection while charge is removed from the floating gate of the PMOS transistor undergoing F-N tunneling. These details are explained further in the above-noted related patent applications.
At the end of a storage operation, there is an imbalance in the threshold voltages (V.sub.T s) of the stacked gate PMOS transistors P.sub.1 and P.sub.2. The V.sub.T of the "OFF" (i.e., non-conducting) PMOS transistor becomes more positive due to BBHE injection while the V.sub.T of the "ON" (i.e., conducting) PMOS transistor tends to become negative due to F-N tunneling current. After the storage operation, Vcc can be removed indefinitely. During this power down time, the difference in the PMOS V.sub.T s will be preserved.
Two features of this storage operation are:
1. The imbalance created in the V.sub.T s of the PMOS transistors are opposite to their current conducting states, i.e., the V.sub.T of the non-conducting PMOS transistor is shifted towards the conducting state and vice-versa.
2. This kind of imbalance may be created for all the cells 100 in an entire memory core 60 during the storage operation.
As further shown in FIG. 4, a non-volatile (NV) recall operation (as described in the above-noted related patent applications) may be performed in two stages. On power up (Phase 1), the PMOS transistor with a less negative V.sub.T becomes conducting or "ON". This was the "OFF" PMOS transistor during the NV storage operation. Thus, on initial power up, the recalled state of cell 100 is the inverse of the cell state during the NV storage operation. To retrieve the original state of cell 100, one more NV storage operation (a "dummy" storage operation) is performed by raising Vcc to Vpp (and lowering Vss to Vnn if desired). This is followed by a power down period (Vcc is removed) and a second power up (Phase 2) during which the supply voltage to the cell 100 raised from 0 to Vcc. Due to the inversion of states during the dummy storage and recall (Phase 2 power up) operations, the state recalled after the Phase 2 power up is the same as the original state when the first storage operation was performed. Thus, the originally stored state of cell 100 is recovered.
Although the "dummy" storage operation allows the original state of memory cell 100 to be recovered, it takes time and also exposes the NVSRAM cell to two high voltage programming cycles, which reduces the reliability of the cell. Accordingly, what is desirable is a new scheme for recovering the originally stored state of an NVSRAM cell.